The present invention relates generally to electronic integrator circuits, and more specifically to an incremental integrate and dump circuit.
Electronic integrator circuits are devices which produce an electronic output signal which is proportional to the integral of the input signals that they receive. Such devices have digital applications in analog-to-digital converters. In such applications, the integrator circuit approximates the mathematical process of integration.
It is often desired to integrate a signal from a previous time, (t-T). to the present time, t, in order to get an average value for the time period, (t-T). This previously has been done by using an integrate and dump circuit. An integrate and dump circuit generally consists of the charging of a capacitor through a resistor end of the period then discharging or dumping the charge on the capacitor to start the next period.
The prior art integrators, as described above, are simple, but require dump circuits to discharge the capacitor after each cycle of use. High speed electronic applications can require the use of integrators over very short periods ranging from 10 to 1,000 nanoseconds. In such applications, it is very difficult to dump the charge on the capacitor of the integrator
The task of providing a high speed incremental integrator is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,030,038 issued to Daniel et al.;
U.S. Pat. No. 3,767,899 issued to L. Barter;
U.S. Pat. No. 3,906,214 issued to R. Hess;
U.S. Pat. No. 4,020,363 issued to S. Numata et al; and
U.S. Pat. No. 4,278,943 issued to E. Basuda et al.
All of the above-cited disclose integration circuits. Of particular note is the system of U.S. Pat. No. 4,030,038 which discloses an integrator circuit having several periodic dumping integrators all sharing the same analog-to-digital converter. U.S. Pat. No. 3,767,899 discloses a digital integrator for evaluating operator selected portions of analog chart traces. U.S. Pat. No. 3,906,214 discloses a signal retaining integrator having the capability of maintaining a reference voltage required for precision integration.
While the systems disclosed in the above-cited references are instructive, the need remains to provide an incremental integrator circuit which outputs a time-averaged value of an analog signal over short intervals without requiring a dump circuit to discharge the integrator. The present invention is intended to satisfy that need.